1. Field of the Invention
The present invention relates to a disparity detection circuit used for a 2-bit to 4-bit coded signal decoder (hereinafter simply called decoder).
In digital signal transmission, a self-timing method is usually used, in which a signal receiver extracts a timing signal from a signal transmitted serially and establishes synchronization with the signal based upon the timing signal. In the self-timing method, however, if a streak of logical-0 bits occurs in a data bit string to be transmitted, without including a logical-1 bit, for example, it is difficult for the receiver to discriminate a timing signal. In order to prevent such inconvenience, a 2-bit to 4-bit (hereinafter called 2B4B) coding rule is widely used in optical terminal repeater equipment or intermediate repeater equipment.
A 2B4B-coded signal decoder decodes a 2B4B-coded signal into an original signal by using a disparity detection circuit which detects disparity of the 2B4B-coded signal.
In order to reduce the cost and, therefore, the amount of circuitry of a 2B4B-coded signal decoder, it is an absolute necessity to reduce the amount of circuitry constituting each functional unit of the signal decoder, including a disparity detection circuit.
Therefore, a disparity detection circuit made of as small amount of circuitry as possible, is in great demand.
2. Description of the Related Art
The 2B4B coding rule is a rule for coding a 2-bit main signal and a 1-bit service signal into a 4-bit signal (hereinafter called 4B signal) according to a 2B4B coding rule (see FIG. 1), with an additional bit added. The main signal consists of 2 bits from a data bit string to be transmitted. The service signal, as the alias service channel denotes, is independent of the main signal and carries additional information, e.g., a particular bit-pattern indicating the heading of a data frame and communication control information to be interchanged between intermediate repeater equipment, for example. FIG. 1 is a coding table illustrating an example of a 2B4B coding rule. Decoding a 2B4B-coded signal (i.e., 4B signal) is performed in such a way that disparity of a 4B signal received is first detected and, based on the disparity, the 4B signal is converted into the original signal (i.e., 2-bit main signal and 1-bit service signal) according to a decoding table in FIG. 2. FIG. 2 is a decoding table illustrating an example of decoding a 4B signal.
Disparity shown in FIGS. 1 and 2 is a value obtained by subtracting the number of logical-0 bits from that of logical-1 bits in the 4B signal received, whose 16 bit-patterns and the corresponding disparity are shown in FIG. 3. FIG. 3 is a table illustrating the disparity for 4B signals. Disparity is any of values "0", "+2", "-2", "+4" and "-4". For example, when 4B signal is "0000", in which the number of logical-1 bits is zero and that of logical-0 bits is 4, the disparity of "0000" is "-4". In the same way, the disparity of "0011", in which the number of logical-1 bits is 2 and that of logical-0 bits is 2, is "0".
An additional bit is added to an original signal (2-bit main signal from data to be transmitted plus 1-bit service signal), and the four bits are coded into a 4B signal according to the FIG. 1-coding table.
When an original signal is any of "001", "010" and "100", an additional logical-1 bit is added after the 3 original signal bits to form a 4B signal, in which the disparity results in "0". When an original signal is any of "011", "101" and "110", a logical-0 bit is added after the 3 original signal bits, in which the disparity results in "0". When an original signal is "000" and the last-occurred disparity except "0" is "+2" or "-2", the 4B signal is "1101" or "0001", respectively. When an original signal is "111" and the last-occurred disparity except "0" is "+2" or "-2", the 4B signal is "1110" or "0010", respectively. 4B signals other than those defined in the FIG. 1-coding table are erroneous since the number of combinations of 3 original signal bits are only 8 as described above. For example, 4B signal "0000" is an error.
In the decoding table shown in FIG. 2, a 4B signal (A1, A2, A3, A4) represents 4 bits into which an original signal is coded at a sending end and received at a receiving end, and a 2B signal (B1, B2, B3) represents 3 bits into which the 4B signal received is to be decoded at the receiving end.
When a 4B signal is a code whose disparity is defined in the FIG. 1-coding table (hereinafter simply called defined) with disparity "0" and the last-occurred status (hereinafter called status-in) is logical 0, the 2B signal is the first 3 bits (excluding the additional bit) from which the 4B signal is coded, at a sending end, according to the FIG. 1-coding table. That is, the 2B signal is the original signal. Then, a current status (hereinafter called status-out) is set to logical 0.
When a 4B signal is defined with disparity "0" and the status-in is logical 1, the 2B signal is the first 3 bits (i.e., the original signal) from which the 4B signal is coded according to the FIG. 1-coding table. The status-out is set to logical 1.
For a defined 4B signal with disparity "+2" and the status-in being logical 0, the 2B signal is the first 3 bits (i.e., the original signal) from which the 4B signal is coded according to the FIG. 1-coding table. The status-out is set to logical 1.
For a defined 4B signal with disparity "+2" and the status-in being logical 1, the 2B signal is A1, A2 and A3 as received. The status-out is set to logical 1.
For a defined 4B signal with disparity "-2" and the status-in being logical 1, the 2B signal is the first 3 bits (i.e., the original signal) from which the 4B signal is coded according to the FIG. 1-coding table. The status-out is set to logical 0.
2B signals and their status-out signals of other 4B signals are as shown in the FIG. 2-decoding table.
Thus, a 4B signal received can be decoded into a corresponding 2B signal by detecting disparity of the 4B signal and, based on the disparity detected, status-in and status-out, by selecting either the first 3 bits (i.e., original signal) from which a 4B signal is coded according to the FIG. 1-coding table or the first 3 bits A1, A2 and A3 as received.
FIG. 4 is a block diagram illustrating a decoder circuit of related art, which decodes a 2B4B-coded signal (i.e., 4B signal) into a 2B signal.
A 4B signal received is supplied to a selector 6a, 2B4B-coded signal decoding circuit (hereinafter called 4B2B decoder) 1a, disparity detector 2a and disparity detector 3a. The 4B2B decoder 1a decodes the 4B signal into an original signal (2-bit main signal and 1-bit service signal) from which the 4B signal is coded according to the FIG. 1-coding table. The disparity detector 2a detects the disparity (-4, +4, -2, +2) of the 4B codes undefined in the FIG. 1-coding table. The disparity detector 3a detects the disparity (0, -2, +2) of the defined 4B signals.
A disparity generator 7a, based on a later-explained status-in signal and the disparity detected by the disparity detectors 2a and 3a, generates a status-out signal (logical 0 or 1) according to the FIG. 2-decoding table. A status holder 4a, which is made of a flip-flop, inputs and holds the status-out signal from the disparity generator 7a.
A selection controller 5a, based on the disparity detected, status-in and status-out and according to the FIG. 2-decoding table, determines which to select, a 3-bit original signal from which a 4B signal is coded or 3 bits A1, A2 and A3 as received, and outputs a select signal indicating which to select.
Thus, the selector 6a, based on the select signal from the selection controller 5a, selects either the original signal from which a 4B signal is coded or 3 bits A1, A2 and A3 as received, thus converting a 4B signal to a 2B signal.
FIG. 5 is a disparity detection circuit of the related art, which is a detailed circuit of the disparity detectors 2a and 3a shown in FIG. 4. The disparity detector 3a portion (enclosed in a broken line) of the disparity detection circuit detects disparity of defined 4B signals and the disparity detector 2a portion (outside the broken line) detects the disparity of undefined 4B signals.
Reference numerals D1, D2, D3 and D4 correspond to A1, A2, A3 and A4 bits of a 4B signal, respectively; XD1, XD2, XD3 and XD4 are the negation of the D1, D2, D3 and D4, respectively.
According to the FIG. 1-coding table, the AND, NAND and NOR gates constituting the disparity detection circuit (or disparity detectors 2a and 3a shown in FIG. 4) perform respective logical operations on the D1-D4, and XD1-XD4 to output signals M2, M1, M13, M3, M0, M4 and MERR, which are low-active. Signals M2, M1, M13 and M3 represent the disparity "0", "-2", ".+-.2" and "+2" of defined 4B signals, respectively. Signals M0 and M4 represent the disparity "-4" and "+4" of undefined 4B signals. Signal MERR represents undefined 4B signals.
Accordingly, the thus-constructed disparity detection circuit of the related art requires as large amount of circuitry as fourteen 4-input AND gates, two 4-input NAND gates, one 4-input NOR gate, three 2-input AND gates, two 2-input NOR gates and one 6-input NOR gate.
A problem is that the disparity detection circuit (i.e., disparity detectors 2a and 3a) of the related art occupies a large part of a 2B4B-coded signal decoder in circuit amount, increasing the cost and the size and reducing the reliability of the 2B4B-coded signal decoder.